1 Implementation of the RASSP SAR Benchmark on the Intel Paragon * Curtis P . Brown Richard A . Games

1 Implementation of the RASSP SAR Benchmark on the Intel Paragon

A software design process for mapping real-time applications onto massively parallel processors is described. The design methodology incorporates a software test bench used to evaluate the level of real-time performance the processing nodes are capable of delivering. The final integration step maintains the simple test bench interfaces and reduces the complexity of integrating the components to...

Real-time Parallel Software Design Case Study: Implementation of the Rassp Sar Benchmark on the Intel Paragon

Design and Implementation of NX Message Passing Using Shrimp Virtual Memory Mapped Communication

This paper describes the design, implementation and performance of the NX message-passing interface on the Shrimp multicomputer. Our implementation exploits Shrimp's virtual memory-mapped communication facility. Unlike traditional methods, our implementation performs buuer management at user level without using a special message-passing processor, and requires no CPU intervention upon message a...

LogP Performance Assessment of Fast Network Interfaces

We present a systematic performance assessment of the hardware and software that provides the interface between applications and emerging high-speed networks. Using LogP as a conceptual framework and Active Messages as the communication layer, we devise a set of communication microbenchmarks. These generate a graphical signature from which we extract the LogP performance parameters of latency, ...

DESIGN AND IMPLEMENTATION OF NX MESSAGE PASSING USING SHRIMP VIRTUAL MEMORY MAPPED COMMUNICATION Richard

| This paper describes the design, implementation and performance of the NX messagepassing interface on the Shrimp multicomputer. Unlike traditional methods, our implementation, exploiting Shrimp's virtual memory-mapped communication facility, performs bu er management at user level without using a special message-passing processor, and requires no CPU intervention upon message arrival in the c...